1. Field of the Invention
The present invention relates to a multi-port static random access memory (SRAM), and in particular to an improved multi-port SRAM with reduced number of transistors and increased read access speed.
2. Discussion of the Related Art
As shown in FIG. 1, a conventional multi-port SRAM includes a data latch unit 10 for latching a data in accordance with an output signal WWDDR from a write word line driver (not shown). In addition, a first port 20 outputs a data from the latch unit 10 to a first read bit line RBL0 and a first read bit bar line RBBL0, respectively, in accordance with a first output signal RWDDR0 from a read word line driver (not shown). A second port 30 outputs a data from the latch unit 10 to a second read bit line RBL1 and a second read bit bar line RBBL1, respectively, in accordance with a second output signal RWDDR1 from the read word line driver (not shown). A third port 40 outputs a data from the latch unit 10 to a third read bit line RBL2 and a third read bit bar line RBBL2, respectively, in accordance with a third output signal RWDDR2 from the read word line driver (not shown). A fourth port 50 outputs a data from the latch unit 10 to a fourth read bit bar line RBL3 and a forth read bit bar line RBBL3, respectively, in accordance with a fourth output signal RWDDR3 from the read word line driver (not shown).
The data latch unit 10 includes a first CMOS inverter 12 and a second CMOS inverter 14. The first CMOS inverter 12 has a first PMOS transistor P1 with its source connected to an electric power Vcc, and a first NMOS transistor N1 with its drain connected to the drain of the first PMOS transistor P1 and its source connected to a ground voltage Vss. The second CMOS inverter 14 has a second PMOS transistor P2 with its source connected to the electric power Vcc, and a second NMOS transistor N2 with its drain connected to the drain of the second PMOS transistor P2 and its source connected to the ground voltage Vss.
The data latch unit 10 also includes a third NMOS transistor N3 and a fourth NMOS transistor N4. The third NMOS transistor N3 has its gate connected to an output signal WWDDR from the write word line driver, its source connected to an output signal from the first CMOS inverter 12, and its drain connected to a write bit line WBL. The fourth NMOS transistor N4 has its gate connected to an output signal WWDDR from the write word line driver (not shown), its source connected to an output signal from the second CMOS inverter 14, and its drain connected to the write bit bar line WBBL.
At this time, the third NMOS transistor N3 and the fourth NMOS transistor N4 are write access transistors. The output signal from the first CMOS inverter 12 is applied to the input terminal of the second CMOS inverter 14, and the output signal from the second CMOS inverter 14 is applied to the input terminal of the first CMOS inverter 12, thereby performing a latching operation.
The first port 20 includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and a eighth NMOS transistor N8. The fifth NMOS transistor N5 has its gate connected to a first output signal RWDDR0 and its drain connected to the first read bit line RBL0. The sixth NMOS transistor N6 has its drain connected to the drain of the fifth NMOS transistor N5, its source connected to the ground voltage Vss, and its gate connected to an output signal from the second CMOS inverter 14. The seventh NMOS transistor N7 has its gate connected to the first output signal RWDDRO from the read word line driver and its drain connected to the first read bit bar line RBBLO. The eighth NMOS transistor N8 has its drain connected to the drain of the seventh NMOS transistor N7, its source connected to the ground voltage Vss, and its gate connected to an output signal from the first CMOS inverter 12.
The second port 30 includes a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, and a twelfth NMOS transistor N12. The ninth NMOS transistor N9 has its gate connected to a second output signal RWDDR1 from the read word line driver (not shown) and its drain connected to the second read bit line RBL1. The tenth NMOS transistor N10 has its drain connected to the ninth NMOS transistor N9, its source connected to the ground voltage Vss, and its gate connected to the output signal from the second CMOS inverter 14. The eleventh NMOS transistor N11 has its gate connected to the second output signal RWDDR1 from the read word line driver and its drain connected to the second read bit bar line RBBL1. The twelfth NMOS transistor N12 has its drain connected to the drain of the eleventh NMOS transistor N11 and its gate connected to the output signal from the first CMOS inverter 12.
The third port 40 includes a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, and a sixteenth NMOS transistor N16. The thirteenth NMOS transistor 13 has its gate connected to a third output signal RWDDR2 from the read word line driver and its drain connected to the third read bit line RBL2. The fourteenth NMOS transistor N14 has its drain connected to the drain of the thirteenth NMOS transistor N13, its source connected to the ground voltage Vss, and its gate connected to the output signal from the second CMOS inverter 14. The fifteenth NMOS transistor N15 has its gate connected to the third output signal RWDDR2 from the read word line driver and its drain connected to the third read bit bar line. The sixteenth NMOS transistor N16 has its drain connected to the drain of the fifteenth NMOS transistor N15, its source connected to the ground voltage Vss, and its gate connected to the output signal from the first CMOS inverter 12.
The fourth port 50 includes a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, and a twentieth NMOS transistor N20. The seventeenth NMOS transistor N17 has its gate connected to a fourth output signal RWDDR3 from the read word line driver and its drain connected to a fourth read bit line RBL3. The eighteenth NMOS transistor N18 has its drain connected to the drain of the seventeenth NMOS transistor N17, its source connected to the ground voltage Vss, and its gate connected to the output signal from the second CMOS inverter 14. The nineteenth NMOS transistor N19 has its gate connected to the fourth output signal RWDDR3 from the read word line driver and its drain connected to the fourth read bit bar line RBBL3. The twentieth NMOS transistor N20 has its drain connected to the drain of the nineteenth NMOS transistor N19, its source connected to the ground voltage Vss, and its gate connected to the output signal from the first CMOS inverter 12.
At this time, the fifth, seventh, ninth, eleventh, thirteenth, fifteenth, seventeenth and nineteenth NMOS transistors N5, N7, N9, N11, N13, N15, N17 and N19 each performs a read access function, and the sixth, eighth, tenth, twelfth, fourteenth, sixteenth, eighteenth and twentieth NMOS transistors N6, N8, N10, N12, N14, N16, N18 and N20 act as driver transistors for driving the read access transistors.
The operation of the conventional multi-port SRAM will now be explained with reference to the accompanying drawings.
First, in the write mode, when an output signal WWDDR from the write word line driver (not shown) is a high level, the third and fourth NMOS transistors N3 and N4 are turned on, and the data inputted through the write bit line WBL and the write bit bar line WBBL are inputted into the output terminals of the first and second CMOS inverters 12 and 14.
In other words, as shown in FIGS. 2B and 2C, when the data signal inputted through the write bit line WBL is changed from a high level to a low level, and the data signal inputted through the write bit bar line WBBL is changed from a low level to a high level, as shown in FIGS. 2D and 2E, the data signals outputted to the output terminals of the first and second CMOS inverters 12 and 14 are changed from the high level to the lower level and from the low level to the high level, respectively. In addition, the first and second CMOS inverters 12 and 14 perform a latching function, and the voltage levels of the output terminals remain a low level and a high level, respectively.
In addition, the read mode is enabled when the output signals RWDDR0 through RWDDR3 from the read word line driver (not shown) maintain a high level, respectively.
As shown in FIG. 3A, when a first output signal RWDDR0 from the read word line driver (not shown) is inputted as a high level signal, the first port 20 performs the reading operation. In addition, the output terminals (first and second nodes A and B) of the first and second CMOS inverters 12 and 14 maintain a low level and a high level, respectively. Also, the sixth NMOS transistor N6 of the first port 20 is turned on, and the eighth NMOS transistor N8 is turned off.
As shown in FIGS. 3D and 3E, the third node C becomes a low level due to the output signals from the sixth NMOS transistor N6 and the eighth NMOS transistor N8, and the fourth node D maintains a high level.
The signals from the third node C and the fourth node D are applied to the first read bit line RBL0 and the first read bit bar line RBBL0 through the fifth NMOS transistor N5 and the seventh NMOS transistor N7 as shown in FIGS. 3F and 3G.
The operations of the second port 30, the third port 40, and the fourth port 50 are similar to that of the first port 20 in accordance with the second through fourth output signals RWDDR1 through RWDDR3 from the read word line driver (not shown).
However, in the conventional multi-port SRAM, in the read mode, since each access transistor is provided with a driver transistor, the surface of the memory cell is increased. Also, because it is impossible to increase the size of the driver transistor, the data reading access speed is limited.